config.h 1.5 KB

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  1. #pragma once
  2. #ifdef PS2_DRIVER_USART
  3. #define PS2_CLOCK_PIN D5
  4. #define PS2_DATA_PIN D2
  5. /* synchronous, odd parity, 1-bit stop, 8-bit data, sample at falling edge */
  6. /* set DDR of CLOCK as input to be slave */
  7. #define PS2_USART_INIT() do { \
  8. PS2_CLOCK_DDR &= ~(1<<PS2_CLOCK_BIT); \
  9. PS2_DATA_DDR &= ~(1<<PS2_DATA_BIT); \
  10. UCSR1C = ((1 << UMSEL10) | \
  11. (3 << UPM10) | \
  12. (0 << USBS1) | \
  13. (3 << UCSZ10) | \
  14. (0 << UCPOL1)); \
  15. UCSR1A = 0; \
  16. UBRR1H = 0; \
  17. UBRR1L = 0; \
  18. } while (0)
  19. #define PS2_USART_RX_INT_ON() do { \
  20. UCSR1B = ((1 << RXCIE1) | \
  21. (1 << RXEN1)); \
  22. } while (0)
  23. #define PS2_USART_RX_POLL_ON() do { \
  24. UCSR1B = (1 << RXEN1); \
  25. } while (0)
  26. #define PS2_USART_OFF() do { \
  27. UCSR1C = 0; \
  28. UCSR1B &= ~((1 << RXEN1) | \
  29. (1 << TXEN1)); \
  30. } while (0)
  31. #define PS2_USART_RX_READY (UCSR1A & (1<<RXC1))
  32. #define PS2_USART_RX_DATA UDR1
  33. #define PS2_USART_ERROR (UCSR1A & ((1<<FE1) | (1<<DOR1) | (1<<UPE1)))
  34. #define PS2_USART_RX_VECT USART1_RX_vect
  35. #endif
  36. #define MATRIX_COL_PINS { F1, F4, F5 }
  37. #define MATRIX_ROW_PINS { F0 }
  38. /* COL2ROW or ROW2COL */
  39. #define DIODE_DIRECTION COL2ROW
  40. #define LOCKING_SUPPORT_ENABLE
  41. #define LOCKING_RESYNC_ENABLE